Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme / 低雜訊低偏移CMOS
博士 / 國立交通大學 / 電子研究所 / 107 / Micro-electromechanical system (MEMS) products are widely used in our daily life. One of them is the MEMS accelerometer. In most cases, measuring the accelerations and the additional signal processing are necessary. The CMOS (Complementary Metal-Oxide-Semiconductor)/MEMS process has the advantage of integration. The process can integrate MEMS devices as well as CMOS circuitry. However, the composite thin-film structure of CMOS/MEMS technology suffers from residual stresses and limits the device’s performance. This thesis presents the design, simulation and mechanical characterization of a newly proposed CMOS/MEMS accelerometer. The monolithic CMOS/MEMS accelerometer was fabricated using the 0.18 μm application-specific integrated circuit (ASIC)-compatible CMOS/MEMS process. The single axis accelerometer was first implemented and the tri-axis accelerometer was later developed. The proposed CMOS/MEMS accelerometer consisted of a proof mass, sensing fingers, springs, and a curl matching frame. The tri-axis single proof mass accelerometer had an area of 1096 μm × 1256 μm, while the single axis accelerometer had an area of 816 μm × 696 μm. The z-axis sensor was embedded in the proof mass of the y-axis and the y-axis sensor was embedded in the proof mass of x-axis sensor. The springs of the x-axis and y-axis were similar to a single axis design. Comparing the three individual sensing units, the tri-axis single proof mass accelerometer reduces 23.77 % of the chip area. To solve the curving problem, the layer combination for residual stress reduction and the curl matching frame are presented. For in-plane sensing, the serpentine spring is used for both single and tri-axis design. For out-plane sensing, the torsion spring is adopted. The sensitivity of accelerometers strongly depends on the spring constants of the suspension system. The stiffness of the spring plays an important role in sensor design. A serpentine spring is adopted in various MEMS sensors. The stiffness of the spring was decided by the width, length and turns of the springs. By analyzing the structure, an approximate analytical model for the spring design is presented. The approximate analytical model for the spring design is experimentally verified. The proposed analytical model can be applied to design related inertial sensors. In this study, two accelerometer designs were evaluated, both theoretically and experimentally. An in-plane vibration analyzer was used to characterize the microstructure. The resonant frequency was detected optically at atmospheric pressure at room temperature with a laser Doppler vibrometer. The resonant frequency of the single axis accelerometer was around 2 kHz. The in-plane resonant frequency of tri-axis accelerometer was around 2.5 kHz. The out-plane resonant frequency of tri-axis accelerometer was around 5.35 kHz. Due to the CMOS/MEMS process limitation, the sensing capacitor of the accelerometers is only few femto farads. The sensing signal may be damaged by electronic noise. Therefore, low noise circuit is needed. Sensor readout circuits for capacitive accelerometers suffer from a signal offset due to production mismatch. This thesis also presents the monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal process. Since flicker noise is inversely proportional to frequency, the operation frequency determines the noise performance. The chopper architecture modulates the signal to chopping frequency to suppress flicker noise. The proposed circuit architecture minimizes the noise figure. Two strategies are applied to lower the noise figure. First, modified the circuit architecture operates the second stage amplifier at 333.33 kHz. Second, the noise factor of the first amplifier is significant for the readout circuit. The telescopic topology is chosen since it has fewer noise-contributing transistors, and hence the noise factor is reduced. The low noise chopper architecture and telescopic topology is developed to achieve low noise. Spectre PNoise simulation is used for noise characterization. The simulation results verify the effectiveness of the proposed reduction architecture. The experiments show noise floor is 421.70 μg/√Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. Standard CMOS process is suitable for implementing digital offset trimming. Hence, the offset trimming mechanism is presented to overcome the offset from sensor and interface circuit. Small capacitor in sub-femto farad scale is placed in parallel with the sensing capacitors to cancel the sensor offsets. A segmented split capacitor structure is proposed to realize sub-femto farad scale capacitor. The 8-bit trimming capacitance is implemented using unit capacitance Cunit. Cunit is around 214.48 fF. The trimming capacitance can compensate up to 21 fF capacitance mismatch which is around ± 8 g sensing capacitance. The trimming capacitor is controlled by the digital value from the evaluation board to eliminate the zero-g offset. The zero-g offset of the system is characterized for the two aspects, static and dynamic operation. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg. The proposed circuit is compactly integrated with the CMOS/MEMS accelerometer structure in a single chip. Proposed monolithic low noise and low zero-g offset CMOS/MEMS accelerometer readout scheme which provides high precision can be used in various wearable applications.
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